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Sliding window inference using FPGA as an accelerator.
For comparison to previous bare metal results on the same hardware
First FPGA implementation of STAC-A2 benchmarks
Multiple records in performance and storage efficiency
Worst pairwise error between 94 ports on 2 devices was 799 picoseconds
Solution sets total of 17 records in scale and baseline benchmarks
Sub-30 nanosecond latency for 68-byte frames
Will head up strategy
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