Latest News

First FPGA implementation of STAC-A2 benchmarks

Multiple records in performance and storage efficiency

Worst pairwise error between 94 ports on 2 devices was 799 picoseconds

Solution sets total of 17 records in scale and baseline benchmarks

Sub-30 nanosecond latency for 68-byte frames.

Will head up strategy

Any chance to help is worthwhile.


About STAC News

Read the latest about research, events, and other important news from STAC.

Subscribe to notifications of research, events, and more.

Enter your email above, then click "Sign Up" to join the STAC mail list and (optionally) register to access materials on the site. Click for terms.