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Designing the right hardware stack for FPGA

At the 19 October 2023 STAC Summit in New York, our panelists discussed "Designing the right hardware stack for FPGA". Panelists were:

The following vendors gave short presentations before the panel discussion:

  "Trade Smarter and Trade Faster with the New AMD FPGA accelerator for Ultra-Low Latency Trading"
    Hamid Reza Salehi, Director Product Marketing, AMD
  "Arista 7130 Update: Ultra Low Latency 25G"
    Darrin Machay, Principal Engineer, Arista

 

Watch the panel discussion below.

Related Event

STAC Summit, 19 October 2023, NYC

NOTE: Some or all of the content on this page and its attachment(s) were supplied by a party other than STAC. STAC does not endorse the content. No performance claims are supported by STAC except those found in an official STAC Report of results audited by STAC.