STAC Summit, 19 October 2023, NYC

STAC Summits

STAC Summits bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical challenges in trading and investment.

New York Marriott Marquis
1535 Broadway
New York
Astor Ballroom
7th Floor


Click on the session titles to view the slides.

STAC Update: Big computeMachine Learning   Big Compute   

Bishop will present the latest STAC Benchmark Council activities compute critical workloads, including STAC-A2 (complex derivatives risk computation) and an update from the STAC-ML Working Group.

Innovation RoundupMachine Learning   Big Data   Fast Compute   Big Compute   
  "How to maximize your GPU investment"
    Jeff Chu, Financial Services Sales, Penguin Solutions
  "Introducing Intel’s discreet GPU’s and ability to co-exist in a heterogeneous environment."
    Bob Gaines, HPC/ AI Technical Solutions Architect, Intel Corporation
  "Data at Scale: Overcoming Challenges in Generative AI and LLM Development"
    Keith Miller, VP Technical Sales, Services and Support, DDN
Building heterogeneous compute pipelinesMachine Learning   Big Data   Fast Compute   Big Compute   

HPC engineers benefit from the growth of compute options by applying the right compute to the right job. Compute-intensive analytic workloads often string together CPUs, GPUs, FPGAs, and purpose-built silicon, each handling a different stage of a larger compute pipeline. But doing so is far from plug-and-play. Architects, system admins, and developers must worry about efficient IO, shared memory access, and interoperability. Should compute grids follow the cloud's lead and disaggregate storage? Should and can memory follow suit? Can we rely on PCIe, or is the network the interconnect of choice? And how do we avoid re-developing the software and building new operational pipelines whenever we add a new accelerator to the mix? Join our panel of experts as they discuss these questions and more.

Waste not, want not: Avoiding idle GPUsMachine Learning   Big Compute   

Many financial firms are looking to large-scale GPU clusters to meet the demands of compute-hungry AI and HPC workloads in price discovery, portfolio management, and quantitative research. But once they fill the compute gap, a knowledge gap remains. How should system engineers and admins best utilize these enormous investments and avoid the pitfalls that result in poor performance? Troy will help us understand how to ensure high availability and maximize the utilization of expensive computing platforms. Using Penguin's experience bringing a 16k GPU cluster online for Meta, he’ll walk us through some real-life issues encountered and solutions applied. Along the way he’ll cover best practices for designing, building, deploying, and managing large-scale GPU clusters.

STAC Update: Time seriesBig Data   Big Compute   

Peter will present the latest results in STAC-M3 (tick analytics).

Innovation RoundupBig Data   Big Compute   
  "Is fast, resilient storage possible in the Cloud? Aeron Cluster’s answer to Cloud Storage Performance"
    Dave Clack, Chief Product Officer, Adaptive
  "KIOXIA SSD and Memory Products for Finance IT"
    Vito Chiarella, Sr. Director, Global Accounts & Datacenter, East Sales, Kioxia
Enforcing the foundation: Improving data lineageMachine Learning   Big Data   Big Compute   

It's no secret that the automation of insights drives forward the financial industry. Both traditional quantitative analysis and newer AI models require a solid data foundation. Data engineers have to build this foundation from an ever-increasing universe of data sets, which come from many sources with varying quality. Even worse, today's data could be corrected tomorrow, next week, or next year. For models to stay stable during rapid innovation, data engineers must properly track, maintain, and leverage the data's lineage. How should they track change sets, version data, and stay synchronized across the enterprise? How should licensing and permissions be taken into account? What are the best practices for maintaining metadata? How do storage architectures impact data lineage solutions? Join our panel of experts and add your questions to the mix. To kick off, some of the panelists provided a short presentation:

  "Mechanics of Low Latency Capture"
    Michael Lehr, Head of Technology, Low Latency, Refinitiv, an LSEG Business
  "Unleash the revenue of your historical data"
   Robert Glanzman, Global Strategic Alliances Principal Architect, Financial Services, Pure Storage
  "Using a vector database to unlock the power of your data"
   Peter Kohler, SVP - Global Head of Presales, KX
The unbearable heaviness of data: Can modern approaches help?Machine Learning   Big Data   Big Compute   

It's common for data architects and engineers to spend more time managing data than creating value from it. They have to deal with data-hungry end users, capture real-time streams, and manage multiple derivative data sets for historical research. AI adoption is piling on troves of model inputs and outputs that are required for explainability and fine tuning. And hybrid cloud infrastructures mean copies in multiple locations. How can architects and engineers enable new value from data rather than simply managing the inventory? Mark has seen financial firms greatly reduce the burden of data maintenance, allowing technologists to focus on developing data products. Using Dell's experience with an international bank as a guide, he'll show how applying an open data platform, from edge to core to cloud, can reduce data movement, consolidate data intelligently, and allow access to diverse tools and uses, all while keeping data secure. Be sure to bring your questions for Mark as he covers best practices in data modernization and the benefits they can bring.

STAC Update: Network communicationsFast Data   Big Data   

Peter will present on the latest STAC Benchmark Council activities in network communications, including recent test results on a high frequency radio link and benchmark development activities for cloud networking.

Innovation RoundupBig Data   Big Compute   
  "Low-latency convolution-based ML inference on market data"
    Liz Corrigan, Head of Engineering,
  "Create a Better and Faster Consolidated View Across Markets Using FPGAs"
    Cliff Maddox, Director of Business Development, NovaSparks
  "Build. Connect. Analyse. Beeks solves your colo and network visibility challenges."
    Matthew Cretney, Head of Product Management, Beeks Group
  "The Smart Way to Configure a Tap Aggregator"
    Mike Galime, Director - Finance and Capital Markets, Keysight Technologies
Encrypting our markets: The impact of security on high-performance infrastructuresFast Data   

Security has become a key component of the systemic risk conversation. Market oversight groups are discussing encrypted connections, and at least one exchange has rolled them out. Encryption can provide a layer of protection, helping prevent threats from moving horizontally through financial systems. But our markets benefit from high-performance, low-friction connectivity. What conflicts can arise when security meets market access? Our panel of experts will discuss how to solve for security without exacerbating other tech risks. They'll dive into important aspects, including what concerns motivate a desire for higher security, what should be in scope, the impact on performance, and how to maintain network-based risk, compliance, and data monitoring systems when encryption is a must. Bring your questions and join us to explore the impact of encryption on market connectivity.

STAC Update: Fast dataFast Data   

Peter will discuss the latest test results for STAC-N1 (full stack networking).

Innovation RoundupFast Data   Fast Compute   
  "Accelerate applications on the Wire"
    Tom Spencer, Business Development and Marketing Professional, Intel Corporation
  "nxFramework update: Added features and improved latency for the Exegy FPGA development framework"
    Laurent de Barry, Sr. Director, Global Head of Solutions Consulting, Exegy
  "Leveraging HATI for high resolution timing to FPGAs."
    Ciaran Kennedy, Sales, Safran
  "Mastering Ultra-Low Latency: The Technical Blueprint of FPGA and Software Hybrid Solutions"
    Jean-François Gagnon, Ultra-Low Latency FPGA Solutions Architect, Orthogone
  "Using Equivalence Checking to Rapidly Evolve Your Design"
    Martin Rowe, Sr. Application Engineer, Siemens
Talent shortages in hardware verification: Can ML plug the gaps?Fast Data   Fast Compute   

As discussed at recent STAC Summits, financial firms suffer from a lack of verification engineers. They can achieve significant latency gains with properly designed and implemented hardware solutions, but a shortage of experienced, skilled personnel causes painful lead times and uncomfortable prioritization decisions. Adam thinks that, given the proper setup, advances in ML can provide some relief by increasing the productivity of current staff. He'll dive into tasks that grind on an engineer's time—like regression optimization, failure triage analysis, and bug localization—and explain how ML can ease the burden. Bring your questions and join him as he discusses using ML to accelerate your FPGA and ASIC verification.

Innovation RoundupFast Data   
  "Trading at the speed of light – Beyond ultra-low latency with Salience Labs"
    Chris Porthouse, Chief Product Officer, Salience Labs
  "LDA goes PCIe: Redefining ultra-low latency for PCIe on LDA Orion boards"
    Vahan Sardaryan, Co-Founder and CEO, LDA Technologies
  "ÜberNIC can do... Can Yours?"
    Seth Friedman, CEO, Liquid-Markets-Solutions
Designing the right hardware stack for FPGAFast Data   Fast Compute   

FGPAs are a go-to component for firms looking to improve their latencies, whether by getting strategies as close to the network as possible or offloading critical workflows from the CPU. But as the best engineers know, FPGAs are but one component of the custom hardware stack that affects performance. Given recent and upcoming changes in that stack, designing the best systems requires answering a number of questions. How do on-board HBM3E and tiering impact memory-intensive applications? Do PCIe 5 and CXL change how we think about accessing compute, memory, and storage? Will new designs that pair ASIC with FPGA open new latency possibilities, and what can we achieve with programmable switches? What's the state of the art with FPGA sharing a fabric with CPU and other compute accelerators? Join our panel of experts as they explore these questions and yours. To kick off, there were some brief presentations:

  "Trade Smarter and Trade Faster with the New AMD FPGA accelerator for Ultra-Low Latency Trading"
    Hamid Reza Salehi, Director Product Marketing, AMD
  "Arista 7130 Update: Ultra Low Latency 25G"
    Darrin Machay, Principal Engineer, Arista