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Adam Sherer, Verification Technology Executive, Cadence, presented this at the 19 October 2023 STAC Summit in New York.
Watch the video below.
Download the slides below.
At the 31 May 2023 STAC Summit in New York, our panelists discussed "FPGAs beyond ultra-low latency?". Panelists were:
The following vendors gave short presentations before the panel discussion:
Watch the panel discussion below.
Adam Sherer, Verification Technology Executive, Cadence Design Systems, presented this at the 31 May 2023 STAC Summit in New York.
Adam Sherer, Verification Technology Executive, Cadence Design Systems, Inc., presented this at the 19 October 2022 STAC Summit in New York.
Adam Sherer, Verification Technology Executive, Cadence Design Systems, Inc., presented this at the 1 June 2022 STAC Summit in New York.
Adam Sherer, Verification Technology Executive, Cadence Design Systems, Inc., presented this at Global STAC Live, Fall 2021.
Q&A
Adam Sherer, Verification Technology Executive, Cadence Design Systems, Inc., presented this at the Global STAC Live, Spring 2020.
