STAC Summit, 19 Oct 2022, NYC

• Peter Nabicht, President, STAC

Peter will present the latest benchmark results for big compute stacks.

• Andrey Rybka, Head of CTO Compute and Cloud Architecture, Bloomberg

Each cloud provider offers a wealth of compute, storage, and workflow options. HPC architects are no longer constrained by in-house equipment or limited by lengthy procurement processes. But the new wealth of options has a downside: figuring out what offerings are right for a given workload. The challenges grow tougher with every new cloud provider added to the mix, including seemingly unlimited combinations of offerings, integrations, and ever-evolving operational tools. Architects seem forced to either conduct lengthy evaluations or settle for sub-optimal solutions. Andrey will share some thoughts on simplifying—while still benefiting from—a multi-cloud approach. He will discuss the challenges his team faced and how they successfully overcame them. He will also present a framework for success that he developed while architecting and deploying Bloomberg’s multi-cloud compute infrastructure. Don’t miss this chance to learn from his team’s experience and find more value from multi-cloud compute.

• Joel Kaufman, Senior Technical Marketing Manager, WEKA

According to many user firms within the STAC community, storage-centric workloads continue to be prime candidates for a cloud or hybrid model and are mostly undergoing a "lift and shift". But once the initial move is complete, how do technologists optimize for performance? What architectures make sense when configuring storage for time series databases and high-performance analytics? Joel will walk us through some real-life examples to answer these questions and more. Along the way, he'll provide information on profiling I/O to help you optimize your cloud-based and hybrid storage systems.

• Peter Nabicht, President, STAC

Peter will present the latest benchmark results from software/hardware stacks for historical time-series analytics.

• Bishop Brock, Head of Research, STAC

Bishop will discuss the latest research and Council activities related to machine learning, including updates on inference and training workloads.

• Rachel Oberman, AI Software Solutions Engineer, Intel Corporation

The primary focus of open source AI software has been functionality and usability. To keep up with users' initial needs, projects have prioritized breadth of coverage, including support for hardware, models, and data-pipeline integrations. But the more AI is used in production environments, the more users' needs are shifting to speed and scale. Rachel thinks that performance is critical for the next generation of open source AI projects. After reviewing the current AI landscape and the challenges data scientists and AI engineers often face when they need to speed up and scale up their production pipelines, she will present key improvements the open source community has provided in response. Using currently available projects, she will show you how to exploit these performance innovations while maintaining functionality, through drop-in replacements and just a few lines of code.

• Sven Oehme, Chief Technology Officer, DDN

Many capital markets technologists have experience optimizing storage architectures for workloads like time-series databases and backtesting. But the training phase of Deep Learning is a different workload, with a complex mix of high-concurrency reads, checkpointing, and random large-block mmaps. The storage stack (client, network, file system, and storage hardware) must cater to these access patterns during initial model training as well as retraining. Otherwise, I/O bottlenecks can leave costly compute resources underutilized and delay model deployment. (Few storage architects want to be responsible for missed business opportunities.) In this talk, Sven will help you design more efficient AI solutions by exploring what happens during DL training from the storage system's point of view. Using lessons from real-world examples, he'll discuss the implications for the storage stack and walk through optimizations for the file system and the rest of the datapath.

• Bhushan Chitlur, Senior Principal Engineer, Datacenter and AI group, Intel

At STAC two years ago, Dr. Matthew Grosvenor gave a primer on competing interconnect standards and explained why he viewed Compute Express Link (CXL) as the strongest contender from a technical standpoint. Having the support of all the major processor and systems vendors hasn’t hurt the standard, either. Today CXL-enabled solutions are starting to ship. What do you need to know? Bhushan will dive deep into CXL, explaining how it works and what advantages it provides. He'll also show how CXL interfaces an FPGA with a CPU, impacts the flow of data, and accelerates storage networking and memory-driven applications like realtime data processing and low-latency trading. Bring your questions and join Bhushan to understand this emerging technology.

• Peter Nabicht, President, STAC

Peter will discuss the latest research and Council activities related to low-latency/high-throughput realtime workloads.

• Pawel Szopinski, VP & Head of Transformation, Specialized Infrastructure, Barclays
• Roman Kostiuk, Vice President, Market Data Technical Services, Societe Generale
• Patrick Flannery, Group Leader, Low Latency, Refinitiv, an LSEG Business
• David Taylor, Co-president & CTO, Exegy

Every trading firm faces a choice in how to support latency-sensitive trading strategies with data, analytics, and execution in a new market: should we build and operate our own software/firmware, delegate it to a vendor, or do some of both? Once made, the decision often lasts many years. Do recent trends in the vendor landscape warrant a rethink on what to buy or whom to buy from? M&A has brought together companies in low-latency market data, order entry, historical tick data and analytics, hardware development, network connectivity, and operational support. The emerging product combinations claim to offer deeper and broader value than before. How close do the new offerings get to the ideal of plug-and-play market access? What sort of latency sensitivities can they serve? Are vendors’ engagement models changing along with the products? How are solutions satisfying rising demands such as cloud delivery and secure access, and how will they evolve as customer needs change? Join our panelists to add your questions to the mix. To kick off, some of the panelists provided a short presentation:

• Peter Nabicht, President, STAC

Peter will present updates from the FPGA special interest group.

• Mark Eslinger, Senior Principal Product Engineer, Digital Verification Technologies, Siemens

As trading strategies requiring ultra-low latency have become more complex, so have the designs firms are implementing in FPGAs. In fact, design size and complexity are outpacing headcount – a recipe for stalled projects, underperforming solutions, and buggy implementations. At a time when it is critical to quickly adapt to fast moving markets, hardware engineers must find a way to step on the gas. The software world relies heavily on continuous integration (CI) to get to market faster, but the approach is still underutilized in hardware. In this talk, Mark will lay out a faster path to “go live” via an easy-to-adopt methodology that maximizes CI throughput, exploits automated, exhaustive RTL code inspection, and assures code quality throughout the development process. Join him to learn ways to accelerate your FPGA projects’ time to first trade.

• Adam Sherer, Verification Technology Executive, Cadence Design Systems, Inc.

A straightforward way to design low-latency hardware is by distributing the performance budget across the system's blocks. The design achieves its latency goals if the performance measured in each block meets its budget in all use cases. But this direct approach may not address all problems. What about synchronization between blocks, a saturated communication infrastructure, or the order of the algorithm? Performance issues in these areas can remain in the dark with a block-level approach. Adam will show how to illuminate each layer of the hardware design and find unanticipated bottlenecks. He'll walk through performance measurement methods you can use immediately at the block, subsystem, and system levels to better understand and improve your performance.

• Todd Strader, FPGA Engineer, Hudson River Trading
• Stephen Kopec, North America, Data Center FAE Manager, AMD
• Darrin Machay, Principal Engineer, Arista Networks

FSI software engineers have long benefited from abundant open-source projects, but firmware engineers still have few good options. This was unsurprising when the developer community was small, but now that FPGA development is widespread in finance and other industries, the time is ripe for change. How can financial firms propel the evolution of open source in FPGA? What projects can benefit from collaboration without participants losing proprietary advantages? In what ways can firms pool resources, work with vendors, and leverage the global community to reduce business costs? What changes are needed to both open- and closed-source toolchains to accelerate collaborative projects? Join our panel of experts as they discuss these questions and yours. To kick off, some of the panelists provided a short presentation: