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Posted April 7, 2024 by jack.gidding

Proposed Test Harness Reviews

In this thread, we will post Test Harnesses designs for STAC-T0 configurations that firms intend to audit. Please post commentary and questions during a one week period following the policy posted at https://stacresearch.com/test-harness-review-procedure 

Comments

Posted on April 8, 2024 by jack.gidding

A vendor is staging a STAC-T0 test for audit using an AMD Alveo UL3524 FPGA board. As per the policy, the harness setup is documented here for community revoew. 

  • The attached diagram (STAC-T0-Setup-STAC-T0_with_qualify.jpg) shows the setup of the test harness (bottom diagram) and the setup for the calculation of error in the latency measurement (top diagram). All connections in the harness are optical fiber. 
  • Timestamping in the SUT is performed by the Arista 7130 MetaWatch.
  • Replay and capture capabilities are provided using the SolarFlare XtremeScale™ SFN8542.
  • A Bill of Materials (STAC-T0_Setup_BOM.pdf) is attached to document all components in the harness setup. The firmware deployed on the AMD board is specific to the vendor sponsoring the test. 

Please provide any comments or questions as a reply to this post within the next week.

File: 
STAC-T0-Setup-STAC-T0_with_qualify.jpg
STAC-T0_Setup_BOM.pdf

The speed with which applications in the trading process (algorithmic "black boxes", matching engines, smart order routers, etc.) can get information from and to the network is a critical--sometimes decisive--contributor to their overall latency. 

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