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Ultra Low Latency Networking with Algo-Logic on Intel PAC D5005 FPGA

John Lockwood, CEO, Algo-Logic, presented this at the Global STAC Live, Spring 2021.

Watch the video below.

Download the slides below.

AttachmentSize
GSL-Spring2021-Algo-Logic.pdf1.29 MB

Related Event

Global STAC Live, Spring 2021

NOTE: Some or all of the content on this page and its attachment(s) were supplied by a party other than STAC. STAC does not endorse the content. No performance claims are supported by STAC except those found in an official STAC Report of results audited by STAC.