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STAC Presummit Sessions, 18 October 2023, NYC

STAC Summits

Presummit Sessions are new in Fall 2023 and occur the day before the STAC Summit New York. They include vendor-led sessions that allow for demos, detailed product explanations, round table discussions, etc. They are open for all financial technologists to attend, but space is limited. More information and the ability to register for each Presummit Session is below.

STAC will also host Working Group meetings during the Presummit Sessions. If you are interested in joining us for those, please contact us.

If you are looking for the STAC Summit agenda and registration,
please find it here.

WHEN
Wednesday, October 18, 2023
1:00pm - 5:00pm EDT
Each ession start time is specified below
Check-in begins at 12:30pm EDT
WHERE
New York Marriott Marquis
1535 Broadway
New York
Empire Complex
7th Floor

PRESUMMIT SESSIONS
(Each session description provided by the sponsor)
1:00pm - 5:00pm Accelerating Development of HFT FPGA and ASIC Systems                      Register Here
 

Cadence provided the following description:
   
"HFT systems implement complex packet processing and trading intelligence optimized for speed. With complexity growing and engineering resources becoming harder to find, new techniques to optimize each stage of development are warranted. It’s generally understood that these new techniques require an investment before they yield a return. But what is the extent of the knowledge and resource investment, what can these new techniques deliver, and what is ROI?

This workshop provides answers to those questions. Together with our HFT advisors, we’ve identified 5 key topics and created technical tutorials for each. The workshop features Cadence subject matter experts who will field your questions as we present each of the topics in these mini-tutorials:

  • Faster coding and optimization with high-level synthesis led by Dr Amzie Adams, Digital Design Technical Executive
  • Get to design confidence faster with comprehensive verification led by Adam Sherer, Verification Technical Executive
  • Stand-up cost-effective ASIC development led by Mike Lafferty, Applications Engineering Group Director
  • Utilize specialized SerDes IP to reduce latency in HFT SoC led by Jeff Galloway, Principal/Co-Founder/SerDes Architect, Silicon Creations
  • Coding SystemVerilog for Simulation Performance led by Adam Sherer, Verification Technical Executive"
There will be a snack break roughly halfway through.
1:00pm - 2:30pm STAC-ML Working Group Meeting                                                                              Contact STAC
 

The STAC-ML Working Group will discuss workload and measurement requirements for new LLM infrastructure benchmarks. This meeting is open to all members of the STAC-ML Working Group. If you'd like to join the Working Group, please contact STAC for more information.
3:00pm - 4:30pm STAC-A2 Working Group Meeting                                                                              Contact STAC
 

The STAC-A2 Working Group will discuss potential updates to the STAC-A2 benchmark specifications. This meeting is open to all members of the STAC-A2 Working Group. If you'd like to join the Working Group, please contact STAC for more information.

 

About STAC Events & Meetings

STAC events bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical challenges in finance.