STAC event content involving AMD

FPGAs beyond ultra-low latency?

At the 31 May 2023 STAC Summit in New York, our panelists discussed "FPGAs beyond ultra-low latency?". Panelists were:

The following vendors gave short presentations before the panel discussion:

	"FPGA Hardware Acceleration in Electronic Trading, AI, and Data Analytics" Matt Certosimo, Data Center FPGA Field Application Engineer, AMD
	"The Edge of the Edge: PCB Latency in Trading Reaction Time" Adam Sherer, Verification Technology Executive, Cadence Design Systems

Watch the panel discussion below.

FPGA Hardware Acceleration in Electronic Trading, AI, and Data Analytics

Matt Certosimo, Data Center FPGA Field Application Engineer, AMD, presented this at the 31 May 2023 STAC Summit in New York.

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Download the slides below.

AMD Together We Advance Financial Services

Davor Frank, Sr. Manager Field Apps Engineering, AMD, presented this at the 31 May 2023 STAC Summit in New York.

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FPGA Hardware Acceleration in Electronic Trading, AI, and Data Analytics

Matt Certosimo, Data Center FPGA Field Application Engineer, AMD, presented this at the 18 May 2023 STAC Summit in Chicago.

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AMD Together We Advance Financial Services

Alastair Richardson, Strategic Business Development Director, Data Center and Communications Group, AMD, presented this at the 18 May 2023 STAC Summit in Chicago.

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AMD Together We Advance Financial Services

Alastair Richardson, Strategic Business Development Director, Data Center and Communications Group, AMD, presented this at the 4 May 2023 STAC Summit in London.

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AMD Together We Advance Financial Services

Alastair Richardson, Strategic Business Development Director, Data Center and Communications Group, AMD, presented this at the 4 April 2023 STAC Summit in Singapore.

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Advancing open source in FPGA

At the 19 October 2022 STAC Summit in New York, our panelists discussed "Low-latency market integration: Time to rethink buy-vs-build?". Panelists were:

The following vendors gave short presentations before the panel discussion:

	"Open-Source Pros & Cons in the FPGA Development Flow" Stephen Kopec, North America, Data Center FAE Manager, AMD
	"Low-latency layer 3 and FPGAs" Darrin Machay, Principal Engineer, Arista Networks