STAC Builder Day, 13 May 2024, NYC

Scaleflux provided the following description of their session:
   
"Are you always looking for ways to tweak your servers for more performance, better latency, or better power efficiency? In this training, you’ll gain valuable insight into the inner workings of SSDs and how to leverage your drives to get more from your servers. We will explore how SSDs are designed and constructed starting from a single NAND cell. Participants will learn the key aspects of NAND operation, how NAND is formed into a storage media, and the major components and responsibilities of a storage controller. Throughout this journey, design trade-offs for different SSD applications will be explored. Attendees will leave with a better intuition of SSD operation and use this knowledge to improve how they evaluate or troubleshoot SSD performance, how that SSD performance can impact (positively and negatively) system and application performance, and better understand how future trends such as QLC or PCIe Gen6 will affect the SSD landscape."

3forge provided the following description of their session:
   
"Developers and quants, come enjoy a 90-minute in-depth workshop with the creator of the 3forge Full Stack Platform which has been adopted by 1,000s of developers worldwide and has become an industry standard for many enterprise use cases. Get familiar with the 3forge full stack platform concept including:

• Dynamic CEP and late subscriber messaging
• Utilizing a federated database for data blending and ETL
• Snapshot/Delta SOW subscription model
• Differences of query planning for an in-memory vs on-disk datastores

Cadence provided the following description of their session:
   
"HFT systems implement complex packet processing and trading intelligence optimized for speed. With complexity growing and engineering resources becoming harder to find, new techniques to optimize each stage of development are warranted. It’s generally understood that these new techniques require an investment before they yield a return. But what is the extent of the knowledge and resource investment, what can these new techniques deliver, and what is ROI?

This workshop provides answers to those questions. Together with our HFT advisors, we’ve identified 5 key topics and created technical tutorials for each. The workshop features Cadence subject matter experts who will field your questions as we present each of the topics in these mini-tutorials:

• Benefits and Cost Management of HFT Accelerators led by Adam Sherer, Verification Technical Executive
• Stand-up cost-effective ASIC development led by Mike Lafferty, Applications Engineering Group Director
• Latency-optimized SerDes PMA for Deployment in 10G & 25G Trading SoCs led by Jeff Lumish, Director of Digital Design, Silicon Creations
• Engineering Power and Signal Integrity for 25G Ethernet in HFT Accelerators led by Lawrence Der, Application Engineering Director, Cadence
• Leveraging AI/ML to Speed HFT Accelerator Development led by Dr Amzie Adams, Digital Design Technical Executive"

Intel provided the following description of their session:
   
"Intel hardware and tools have been evolving at a rapid pace. If you program in C++, Java, or Python and it has been a while since you learned about ways to improve performance, this is your chance to level up your knowledge--and your code.

Through a combination of live demos and highly interactive tutorials, this half-day session will teach you how to get the most performance and efficiency for high-throughput applications like risk and pricing, back testing, simulation, and electronic trading, whether it runs on prem or in the cloud.

The focus is the Intel oneAPI Toolkit, a performance optimization toolchain widely used by financial service companies. In particular, we will roll up our sleeves and cover how to:

• Zero in on the biggest opportunities to improve the performance of your code on CPU and GPU using VTune profiling
• Leverage highly optimized, parallelized routines for math functions (e.g., BLAS, vectors, RNG, numerical reproducibility) using Intel’s extensive Math Kernel Library
• Reduce compile time, support heterogeneous computing, and sanitize code by transitioning from classic ICC to the LLVM-based ICX
• Auto-migrate existing CUDA code to cross-platform code that runs on Intel, Nvidia, and AMD GPUs with negligible performance degradation
• Accelerate AI inference by leveraging the Intel AMX & XMX engines built into Xeon & Data Center GPU max

• Jeff Reinemann, VTune Technical Consulting Engineer
• Fengrui Zhang, Compiler and Libraries Technical Consulting Engineer
• Ashish Gupta, Software Business Development"