STAC Summit, 1 Nov 2022, Chicago

• Peter Nabicht, President, STAC

Peter will present the most recent results from enterprise tick analytics and market risk.

• Joseph Steiner, Global CTO of Financial Services, UDS Division, Dell Technologies

Financial firms often want to analyze data in a different location from where they capture it, especially as cloud offerings increase the number of potential analysis locations. So technologists must make data mobile while continuing to ensure that it is accessible with high performance. This is already a tough ask and will only get tougher. Data sets are rapidly expanding, while the number of compute locations and their suitability to different tasks will continue to evolve. What are systems architects to do? Joe has an approach for meeting these moving targets. His framework starts with assessing the characteristics and data-usage patterns of a given workload to determine if it would benefit from a hyper-converged infrastructure, what compute accelerators it needs, and if it is better off in the cloud, cloud adjacent, or fully on-premises. The framework incorporates these answers to guide architectural decisions that help make massive data stores both mobile and ready for multiple use cases, current and future. Join us to see how Joe’s framework applies to your needs.

• Peter Nabicht, President, STAC

Peter will discuss the latest research and Council activities related to machine learning, including updates on inference and training workloads.

• Keith Miller, Vice President Technical Sales, Service & Support, DDN

Many capital markets technologists have experience optimizing storage architectures for workloads like time-series databases and backtesting. But the training phase of Deep Learning is a different workload, with a complex mix of high-concurrency reads, checkpointing, and random large-block mmaps. The storage stack (client, network, file system, and storage hardware) must cater to these access patterns during initial model training as well as retraining. Otherwise, I/O bottlenecks can leave costly compute resources underutilized and delay model deployment. (Few storage architects want to be responsible for missed business opportunities.) In this talk, Keith will help you design more efficient AI solutions by exploring what happens during DL training from the storage system's point of view. Using lessons from real-world examples, he'll discuss the implications for the storage stack and walk through optimizations for the file system and the rest of the datapath.

• Peter Nabicht, President, STAC

Peter will discuss the latest research and Council activities related to low-latency/high-throughput realtime workloads.

• Tamir Ostfeld, Deputy CEO and COO, Raft Technologies

Microwave communication is highly dependent on short segments and line of sight. The more distance a link requires, the less applicable microwave is. Enter high-frequency (HF) radio, a longer wavelength signal that can work across thousands of kilometers between towers. HF opens up new possibilities for low latency over long hauls. However, HF is not without challenges. The day-night cycle, impacts of the seasons, solar cycles, and sunspots all affect it. How—and how often—do these physical phenomena impact HF service availability and performance? How many hours per day are HF links available? Where are we in the current solar cycle, and what does that mean for the coming years? What improvements are mitigating these issues? What is the impact on operations for HF adopters? Tamir will address these questions and yours in this interactive session.

• Ian Hutchinson, Markets Technology, a global bank
• Manisha Kimmel, Head of Low Latency Business Integration, Refinitiv, an LSEG Business
• Laurent de Barry, Director, Hardware Trading Solutions, Exegy

Every trading firm faces a choice in how to support latency-sensitive trading strategies with data, analytics, and execution in a new market: should we build and operate our own software/firmware, delegate it to a vendor, or do some of both? Once made, the decision often lasts many years. Do recent trends in the vendor landscape warrant a rethink on what to buy or whom to buy from? M&A has brought together companies in low-latency market data, order entry, historical tick data and analytics, hardware development, network connectivity, and operational support. The emerging product combinations claim to offer deeper and broader value than before. How close do the new offerings get to the ideal of plug-and-play market access? What sort of latency sensitivities can they serve? Are vendors’ engagement models changing along with the products? How are solutions satisfying rising demands such as cloud delivery and secure access, and how will they evolve as customer needs change? Join our panelists to add your questions to the mix.

• Peter Nabicht, President, STAC

Peter will present updates from the FPGA special interest group.

• Adam Sherer, Verification Technology Executive, Cadence Design Systems, Inc.

A straightforward way to design low-latency hardware is by distributing the performance budget across the system's blocks. The design achieves its latency goals if the performance measured in each block meets its budget in all use cases. But this direct approach may not address all problems. What about synchronization between blocks, a saturated communication infrastructure, or the order of the algorithm? Performance issues in these areas can remain in the dark with a block-level approach. Adam will show how to illuminate each layer of the hardware design and find unanticipated bottlenecks. He'll walk through performance measurement methods you can use immediately at the block, subsystem, and system levels to better understand and improve your performance.

• Ben Maron, FPGA Team Lead, Hudson River Trading
• Daniel Wisehart, FPGA & ASIC Engineer
• Matt Certosimo, Data Center FPGA Field Application Engineer, AMD
• Dr. David Snowdon, Director of Engineering, Arista Networks

FSI software engineers have long benefited from abundant open-source projects, but firmware engineers still have few good options. This was unsurprising when the developer community was small, but now that FPGA development is widespread in finance and other industries, the time is ripe for change. How can financial firms propel the evolution of open source in FPGA? What projects can benefit from collaboration without participants losing proprietary advantages? In what ways can firms pool resources, work with vendors, and leverage the global community to reduce business costs? What changes are needed to both open- and closed-source toolchains to accelerate collaborative projects? Join our panel of experts as they discuss these questions and yours. To kick off, some of the panelists provided a short presentation: