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FPGA Accelerators: How to beat RTL design latency with C++ in a fraction of the time

Stephane Gauthier, Product Manager, Silexica, presented this at the Global STAC Live, Spring 2020.

Watch the video below.

Download the slides below.

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GSL-Spring-2020-Silexica.pdf312.6 KB

Related Event

Global STAC Live, Spring 2020

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