Vault report: STAC-M1 results of SR Labs MIPS on Everest and Westmere processors

STAC studies SR Labs feed handler on Everest and Westmere processors.

13 June 2011 - New York

SR Labs is sponsoring a research project into the performance of SR Labs Market Data In Process System market data feed handling software on two of the latest Intel processors, the X5687 (formerly code named Westmere) and the X5698 (formerly codenamed Everest).

MIPS is an in-process, low-latency, low-footprint solution for integrating market data into high- speed trading applications. MIPS feed handlers have been optimized for strategies deployed in exchange co-location (“colo”) hosting.

The Intel X5698 is a unique version of the standard Intel Xeon processor 5600 series, sporting two cores at 4.4 GHz each. Intel says this processor offers the highest frequency and lowest latency of any Intel Xeon processor while still meeting Intel’s rigorous reliability standards.

The two “stacks under test” are as follows:

Specs: STAC-M1

Type: Audited

• SR Labs MIPS In-Process Market Data Line Handler for TVITCH 4.1
• CentOS 5.5, 64-bit
• IBM x3650 Server
• Myricom 10G-PCIE2-8B2-2S NIC
• Processor:
SUT A: 2 x quad core Intel Xeon 5687 3.60 GHz (“Westmere”)
SUT B: 2 x dual core Intel Xeon 5698 4.40 GHz (“Everest”)

The test harness for this project incorporated TS-Associates’ TipOff and Simena F16 Fiber Optic Tap for wire-based observation, along with TS-Associates’ Application Tap cards for precise in-process observation. A Symmetricom SyncServer S350 was the time source for the harness.

Results from the first test case showed an 22% reduction in mean latency when moving from Westmere to Everest. This case involved a TVITCH 4.1 1Gbps datastream played at two times market rate, and a single market data consumer viewing 20% of the instruments on the feed (spec ID: STAC-M1.v2?1.TVITCH41-1G.CLIENT_BASE). Additional test cases will measure the maximum throughput, as well as the maximum watchlist capacity of a single client, along with the latency statistics at those maxima.

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