STAC Summit, 9 November 2023, London

• Bishop Brock, Head of Research, Strategic Technology Analysis Center

Bishop will present the latest STAC Benchmark Council activities compute critical workloads, including STAC-A2 (complex derivatives risk computation) and an update from the STAC-ML Working Group.

• Paul Wallace, Product Marketing Director, DDN
• Jordan Nanos, Machine Learning Architect, Hewlett Packard Enterprise
• Evgueny Khartchenko, Intel Optimization and Software Enabling Engineer, Intel Corporation

HPC engineers benefit from the growth of compute options by applying the right compute to the right job. Compute-intensive analytic workloads often string together CPUs, GPUs, FPGAs, and purpose-built silicon, each handling a different stage of a larger compute pipeline. But doing so is far from plug-and-play. Architects, system admins, and developers must worry about efficient IO, shared memory access, and interoperability. Should compute grids follow the cloud's lead and disaggregate storage? Should and can memory follow suit? Can we rely on PCIe, or is the network the interconnect of choice? And how do we avoid re-developing the software and building new operational pipelines whenever we add a new accelerator to the mix? Join our panel of experts as they discuss these questions and more. To kick off, some of the panelists provided a short presentation:

• Peter Nabicht, President, Strategic Technology Analysis Center

Peter will present the latest results in STAC-M3 (tick analytics).

• Charles Reindorf, Head of Global Markets Data Management, Bank of America
• Fercan Yalinkilic, Product Manager, Low Latency, Refinitiv, an LSEG Business
• Joel Kaufman, Senior Technical Marketing Manager, WEKA
• Prasad Shinde, Solutions Architect / Lead Specialist, KX

It's no secret that the automation of insights drives forward the financial industry. Both traditional quantitative analysis and newer AI models require a solid data foundation. Data engineers have to build this foundation from an ever-increasing universe of data sets, which come from many sources with varying quality. Even worse, today's data could be corrected tomorrow, next week, or next year. For models to stay stable during rapid innovation, data engineers must properly track, maintain, and leverage the data's lineage. How should they track change sets, version data, and stay synchronized across the enterprise? How should licensing and permissions be taken into account? What are the best practices for maintaining metadata? How do storage architectures impact data lineage solutions? Join our panel of experts and add your questions to the mix. To kick off, some of the panelists provided a short presentation:

• Simon Haywood, Field CTO, Dell Technologies

It's common for data architects and engineers to spend more time managing data than creating value from it. They have to deal with data-hungry end users, capture real-time streams, and manage multiple derivative data sets for historical research. AI adoption is piling on troves of model inputs and outputs that are required for explainability and fine tuning. And hybrid cloud infrastructures mean copies in multiple locations. How can architects and engineers enable new value from data rather than simply managing the inventory? Simon has seen financial firms greatly reduce the burden of data maintenance, allowing technologists to focus on developing data products. Using Dell's experience with an international bank as a guide, he'll show how applying an open data platform, from edge to core to cloud, can reduce data movement, consolidate data intelligently, and allow access to diverse tools and uses, all while keeping data secure. Be sure to bring your questions for Simon as he covers best practices in data modernization and the benefits they can bring.

• Peter Nabicht, President, Strategic Technology Analysis Center

Peter will present on the latest STAC Benchmark Council activities in network communications, including recent test results on a high frequency radio link and benchmark development activities for cloud networking.

• Sergej Teverovski, Head of Section, Eurex
• Dipin Divakaran, eTrading Infrastructure Lead, Standard Chartered Bank
• Diana Stanescu, Director Finance and Capital Markets, Keysight Technologies

Security has become a key component of the systemic risk conversation. Market oversight groups are discussing encrypted connections, and at least one exchange has rolled them out. Encryption can provide a layer of protection, helping prevent threats from moving horizontally through financial systems. But our markets benefit from high-performance, low-friction connectivity. What conflicts can arise when security meets market access? Our panel of experts will discuss how to solve for security without exacerbating other tech risks. They'll dive into important aspects, including what concerns motivate a desire for higher security, what should be in scope, the impact on performance, and how to maintain network-based risk, compliance, and data monitoring systems when encryption is a must. Bring your questions and join us to explore the impact of encryption on market connectivity.

• Peter Nabicht, President, Strategic Technology Analysis Center

Peter will discuss the latest test results for STAC-N1 (full stack networking).

• Michael O’Sullivan, Engineering Director, Cadence

As discussed at recent STAC Summits, financial firms suffer from a lack of verification engineers. They can achieve significant latency gains with properly designed and implemented hardware solutions, but a shortage of experienced, skilled personnel causes painful lead times and uncomfortable prioritization decisions. Michael thinks that, given the proper setup, advances in ML can provide some relief by increasing the productivity of current staff. He'll dive into tasks that grind on an engineer's time—like regression optimization, failure triage analysis, and bug localization—and explain how ML can ease the burden. Bring your questions and join him as he discusses using ML to accelerate your FPGA and ASIC verification.

• Denis Luzan, SVP, High Performance Architectures, Citigroup
• César Carpinteiro, Team Lead FPGA, Flow Traders
• Robert DeWitt, Director Product Marketing, AMD
• Olivier Cousin, Director, FPGA Solutions, Exegy

FGPAs are a go-to component for firms looking to improve their latencies, whether by getting strategies as close to the network as possible or offloading critical workflows from the CPU. But as the best engineers know, FPGAs are but one component of the custom hardware stack that affects performance. Given recent and upcoming changes in that stack, designing the best systems requires answering a number of questions. How do on-board HBM3E and tiering impact memory-intensive applications? Do PCIe 5 and CXL change how we think about accessing compute, memory, and storage? Will new designs that pair ASIC with FPGA open new latency possibilities, and what can we achieve with programmable switches? What's the state of the art with FPGA sharing a fabric with CPU and other compute accelerators? Join our panel of experts as they explore these questions and yours.