STAC Summit, 31 October 2023, Chicago

STAC Summits

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STAC Summits bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical challenges in trading and investment.

Tuesday, October 31, 2023
STAC Exchange (Exhibits) opens at 8:30am CDT
Conference starts at 9:00am CDT
Networking lunch at ~12:00pm CDT
Conference concludes at ~4:00pm CDT
Reception immediately following
The Metropolitan Club
Willis Tower
233 South Wacker Drive
66th Floor

(The following are not in order. More to be announced shortly.)
Waste not, want not: Avoiding idle GPUs

  • Troy Kaster, VP of AI, Penguin Computing

Many financial firms are looking to large-scale GPU clusters to meet the demands of compute-hungry AI and HPC workloads in price discovery, portfolio management, and quantitative research. But once they fill the compute gap, a knowledge gap remains. How should system engineers and admins best utilize these enormous investments and avoid the pitfalls that result in poor performance? Troy will help us understand how to ensure high availability and maximize the utilization of expensive computing platforms. Using Penguin's experience bringing a 16k GPU cluster online for Meta, he’ll walk us through some real-life issues encountered and solutions applied. Along the way he’ll cover best practices for designing, building, deploying, and managing large-scale GPU clusters.

The unbearable heaviness of data: Can modern approaches help?
  • Vrashank Jain, Sr. Director of Product Management for Data Management Solutions, Dell Technologies

It's common for data architects and engineers to spend more time managing data than creating value from it. They have to deal with data-hungry end users, capture real-time streams, and manage multiple derivative data sets for historical research. AI adoption is piling on troves of model inputs and outputs that are required for explainability and fine tuning. And hybrid cloud infrastructures mean copies in multiple locations. How can architects and engineers enable new value from data rather than simply managing the inventory? Vrashank has seen financial firms greatly reduce the burden of data maintenance, allowing technologists to focus on developing data products. Using Dell's experience with an international bank as a guide, he'll show how applying an open data platform, from edge to core to cloud, can reduce data movement, consolidate data intelligently, and allow access to diverse tools and uses, all while keeping data secure. Be sure to bring your questions for Vrashank as he covers best practices in data modernization and the benefits they can bring.

Talent shortages in hardware verification: Can ML plug the gaps?

  • Adam Sherer, Verification Technology Executive, Cadence

As discussed at recent STAC Summits, financial firms suffer from a lack of verification engineers. They can achieve significant latency gains with properly designed and implemented hardware solutions, but a shortage of experienced, skilled personnel causes painful lead times and uncomfortable prioritization decisions. Adam thinks that, given the proper setup, advances in ML can provide some relief by increasing the productivity of current staff. He'll dive into tasks that grind on an engineer's time—like regression optimization, failure triage analysis, and bug localization—and explain how ML can ease the burden. Bring your questions and join him as he discusses using ML to accelerate your FPGA and ASIC verification.

Encrypting our markets: The impact of security on high-performance infrastructures

  • Speakers to be announced

Security has become a key component of the systemic risk conversation. Market oversight groups are discussing encrypted connections, and at least one exchange has rolled them out. Encryption can provide a layer of protection, helping prevent threats from moving horizontally through financial systems. But our markets benefit from high-performance, low-friction connectivity. What conflicts can arise when security meets market access? Our panel of experts will discuss how to solve for security without exacerbating other tech risks. They'll dive into important aspects, including what concerns motivate a desire for higher security, what should be in scope, the impact on performance, and how to maintain network-based risk, compliance, and data monitoring systems when encryption is a must. Bring your questions and join us to explore the impact of encryption on market connectivity.

Designing the right hardware stack for FPGA

  • Speakers to be announced

FGPAs are a go-to component for firms looking to improve their latencies, whether by getting strategies as close to the network as possible or offloading critical workflows from the CPU. But as the best engineers know, FPGAs are but one component of the custom hardware stack that affects performance. Given recent and upcoming changes in that stack, designing the best systems requires answering a number of questions. How do on-board HBM3E and tiering impact memory-intensive applications? Do PCIe 5 and CXL change how we think about accessing compute, memory, and storage? Will new designs that pair ASIC with FPGA open new latency possibilities, and what can we achieve with programmable switches? What's the state of the art with FPGA sharing a fabric with CPU and other compute accelerators? Join our panel of experts as they explore these questions and yours.

STAC Updates

STAC will present the latest research, audit results, and STAC Benchmark Council activities compute-intensive derivatives risk calculations, high-speed analytics on time series data, low-latency network communication, and machine learning.

Innovation Roundups
  "GPU Performance and Availability"
   Jeff Chu, Financial Services Sales, Penguin Computing
  "Trade Smarter and Trade Faster with the New AMD FPGA accelerator for Ultra-Low Latency Trading"
   Hamid Reza Salehi, Director Product Marketing, AMD
  "Arista 7130 Update: Ultra Low Latency 25G"
   Darrin Machay, Principal Engineer, Arista
  "Data at Scale: Overcoming Challenges in Generative AI and LLM Development"
   Keith Miller, VP Technical Sales, Services and Support, DDN
  "Mechanics of Low Latency Capture"
   Pramod Nayak, Director of Product Management, Low Latency, Refinitiv, an LSEG Business
  "The Smart Way to Configure a Tap Aggregator"
   Kevin Formby, VP Finance and Capital Markets, Keysight Technologies
  "Is fast, resilient storage possible in the Cloud? Aeron Cluster’s answer to Cloud Storage Performance"
   Fergus Keenan, Chief Strategy Officer, Adaptive
  "Build. Connect. Analyse. Beeks solves your colo and network visibility challenges."
   Matthew Cretney, Head of Product Management, Beeks Group
  "Create a Better and Faster Consolidated View Across Markets Using FPGAs"
   Cliff Maddox, Director of Business Development, NovaSparks
  "Mastering Ultra-Low Latency: The Technical Blueprint of FPGA and Software Hybrid Solutions"
   Jean-François Gagnon, Ultra-Low Latency FPGA Solutions Architect, Orthogone
  "Cancel on Behalf is a Game Changer"
   John Hagerman, VP Marketing and Business Development, Algo-Logic
  "Trading at the speed of light – Beyond ultra-low latency with Salience Labs"
   Chris Porthouse, Chief Product Officer, Salience Labs
  "Leveraging HATI for high resolution timing to FPGA’s."
   Ciaran Kennedy, Sales, Safran Timing & Navigation

And more to be announced from AMD, Exegy, KX, Liquid-Markets-Solutions, and Siemens.

Other topics to be announced

Stay tuned for additional session announcements on a variety of HPC, low latency, and operational efficiency topics.


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About STAC Events & Meetings

STAC events bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical challenges in finance.

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