FPGA Accelerators: How to beat RTL design latency with C++ in a fraction of the time

Stephane Gauthier, Product Manager, Silexica, presented this at the Global STAC Live, Spring 2020.

Watch the video below.

Download the slides below.

AttachmentSize
GSL-Spring-2020-Silexica.pdf312.6 KB

NOTE: Some or all of the content on this page and its attachment(s) were supplied by a party other than STAC. STAC does not endorse the content. No performance claims are supported by STAC except those found in an official STAC Report of results audited by STAC.